Charge pump circuit and non-volatile memory using the same

ABSTRACT

The present invention allows different stepped-up voltages and different output currents to be generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. The present invention provides a semiconductor integrated circuit device which, in one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.

CLAIM OF PRIORITY

The present application claims priority from Japanese application JP2004-077757, filed on Mar. 18, 2004, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a charge pump circuit that generatesthe high voltages required for data erase and read/write operations on anon-volatile memory such as a flash memory, and to a semiconductorintegrated circuit using the same.

2. Description of the Related Art

To use a tunneling effect or hot electrons and/or hot holes during eraseand/or write operations, a high voltage needs to be generated innon-volatile memories such as a flash memory or an EEPROM (ElectricallyErasable Programmable Read-Only Memory).

Electrically rewritable EEPROMs include a metal-oxide nitride-oxidesemiconductor (MONOS) type of EEPROM, and the operating biases in theerase, write, and read modes of the MONOS-type EEPROM that usesMONOS-structured memory cells and enhanced N-type switch metal-oxidesemiconductors (MOS's) to construct a one-bit data pattern are shown inFIG. 1 by way of example.

The operating biases in FIG. 1 are for a power supply voltage of Vdd=1.5V. In this case, the memory cells in erase mode take a threshold voltagevalue (Vt) less than 0 V, and the memory cells in write mode take a Vtvalue of 0 V or more.

Accordingly, since in read mode, applying 0 V to a memory gate (Mg) and1.5 V to a selected switch MONOS control gate (Cg) turns on the switchMOS, whether the data bit is “1” or “0” has been judged by, in the erasemode of the associated memory cell, detecting that a current flows froma bit line (precharged to about 1 V) through that memory cell into asource line and the potential of the bit line decreases. Also, in thewrite mode of the memory cell, the above judgment has been conducted bydetecting that the potential of the bit line precharged to about 1 V isretained. In this case, H-Z shown in FIG. 1 denotes high impedance.

Such a Dickson-type charge pump circuit as introduced and analyzed inthe article of T. Tanzawa and T. Tanaka, “A dynamic analysis of theDickson charge pump circuit,” IEEE J. Solid-State Circuits, vol. 32, no.8, pp. 1231-1240, August 1997, is generally known as an example of acharge pump circuit for generating the high voltage required for eraseand/or write operations. The Dickson charge pump circuit is commonlyused because of its simple circuit composition.

Although EEPROMs have long been frequently used in data updateapplications, further extension of EEPROMs in capacity is being desiredin recent years in order to respond to the diversity of applicationsoftware and the growing tendency for multiple application programs tobe designed so that they operate in one LSI or one system.

Japanese Patent Nos. 1876108 and 1950956 propose MONOS memories withoutan enhanced N-type switch MOS (i.e., single-MONOS memories), partlybecause such extension of capacity is obstructed by the fact that thememory size per bit is too large.

The biases in the operation modes of one such single-MONOS memory areshown in FIG. 2. As can be seen from FIG. 2, the operating biases inerase and write modes are almost the same as for the conventional MONOSmemory shown in FIG. 1, whereas, in read mode, a negative voltage oferase Vt or less needs to be applied to the memory Well and non-selectedMg.

Additionally, although all voltages to be applied to the memory may beset to 0 V in standby mode, startup from standby mode requires a timefrom several microseconds to tens of microseconds in order to obtain astepped-up negative voltage that allows reading. Also a negative voltageis therefore to be applied in standby mode to increase the startupspeed. In this case, symbol H-Z shown in FIG. 2 denotes high impedance.

When the size of a module type of such single-MONOS memory, includingthe size of a peripheral circuit, is considered, the memory itself canbe downsized by deleting the switch MOS. However, a stepped-up negativevoltage must also be applied in read mode and thus a charge pump circuitfor reading is required. In addition, this charge pump circuit forreading needs to be increased in current supply capability so as to becapable of withstanding high-speed reading at about tens of megahertz.

In that case, in addition to the charge pump circuit for erase and writemodes, a read-only charge pump circuit high in current supply capabilityis required, whereby it is likely to increase the total charge pumpcircuit size.

Additionally, since standby mode, as with read mode, makes it necessaryto apply a stepped-up negative voltage, there is also a need to operatethe associated charge pump circuit in standby mode, and for this reason,current consumption could increase in standby mode.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide atechnique that allows area reduction and current-consumption reductionof a charge pump circuit for generating a plurality of stepped-upvoltages different from each other in current supply capability.

The foregoing and other objects and novel features of the presentinvention will become apparent from the description given in thisSpecification, and from the accompanying drawings.

The following briefly describes the gist of the typical one of thepresent inventions disclosed in this application.

The present invention provides a semiconductor integrated circuit devicewhich, in one charge pump circuit with an N number of basic pump cellstages connected to step up voltages in the erase and write modes of anon-volatile memory, generates stepped-up voltages lower than in theerase and write modes and different from one another in output currentsupply capability, by using series- or parallel-connected pump cells notin excess of the N number of pump cell stages mentioned above, andchanges a voltage step-up clock to a stepped-up voltage detectionsignal.

Accordingly, stepped-up voltages each different in output current supplycapability and lower than in erase and write modes can be generated witha single charge pump circuit without causing an increase in charge pumpcircuit area, and a charge pump clock circuit can be deactivated. Acharge pump circuit with reduced current consumption can therefore becomposed.

The following briefly describes the gist of the typical advantageouseffects of the present invention disclosed in this application:

(1) It is possible to construct power supplies different in stepped-upvoltage and in output current, and thus to reduce a chip area.

(2) A charge pump circuit very low in current consumption can becomposed by using a step-up detection signal as a charge pump clock.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the operating biases in each mode of aconventional MONOS-type EEPROM;

FIG. 2 is a diagram showing the operating biases in each mode of aconventional single MONOS-type EEPROM;

FIG. 3 is a diagram showing the composition of a charge pump circuitaccording to the present invention;

FIG. 4 is a diagram showing the circuit composition of charge pump cellsin the charge pump circuit of the present invention;

FIG. 5 is a diagram showing the charge pump circuit composition per pumpcell stage according to the present invention;

FIG. 6 is a diagram that shows specifications of a charge pump circuithaving a 64-KB single MONOS-type EEPROM;

FIG. 7 is a diagram showing the Vpp simulation waveform occurring duringerase/write operations in the charge pump circuit of the presentinvention;

FIG. 8 is a diagram showing the simulation waveform occurring duringread operations in the charge pump circuit of the present invention;

FIG. 9 is a diagram showing the simulation waveform occurring duringstandby (Stby) operations in the charge pump circuit of the presentinvention; and

FIG. 10 is a circuit configuration diagram of the charge pumps in thecharge pump circuit of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described indetail below with reference to the accompanying drawings. In all figuresexplaining the embodiments, the same symbol is assigned to the samemember and repeated description thereof is omitted.

First Embodiment

FIG. 3 shows a configuration example of a charge pump circuit whichapplies a stepped-up bias to a memory cell.

The charge pump circuit of the present invention includes a charge pump,a clock generator circuit, and a stepped-up voltage (Vpp) detectorcircuit for detecting Vpp.

The clock generator circuit, although composed using a general ringoscillator, is not limited by this configuration and may have any otherfunction that allows a clock to be supplied to the charge pump. Thecharge pump is to generate a stepped-up voltage in synchronization withthe clock.

After the charge pump has received the clock and started operating, astepped-up voltage is generated, and when this voltage reaches a definedvoltage value, the Vpp detector circuit detects the voltage value andgenerates Vpp DET as a Vpp detection signal.

The Vpp detector circuit includes a comparator, a reference voltage, andresistors, and generates Vpp DET by comparing the reference voltage andVpp which has been voltage-divided by the resistors. The generation ofVpp DET here means changing a comparator output, for example, from 0 Vto Vpp.

After receiving Vpp DET, the clock generator circuit deactivates theclock. The deactivation of the clock stops a voltage stepping-upoperation of the charge pump.

When the voltage stepping-up operation is stopped, the stepped-upvoltage is reduced below the defined voltage value and the generation ofVpp DET is stopped.

The stop of Vpp DET generation activates the clock generator circuitonce again, supplies the clock to the charge pump, and operates thecharge pump to step up the voltage.

This sequence is repeated to keep the defined voltage step-up value.

FIG. 4 is a charge pump configuration diagram showing a Dickson-typecharge pump circuit in which 13 pump cell stages are connected in seriesusing a charge capacitance of 14 pF to make the circuit free fromsubstrate effects.

A brief, operational description of the circuit shown in FIG. 4 is givenbelow using FIG. 10. In Erase and Write modes, all switches areconnected to an upper (“a”) position and an N number of stages areconnected in series.

The brackets “[ ]” in [N/2] shown in FIG. 10 mean a Gauss' notation, inwhich, when N is odd-numbered, this indicates (N−1)/2 and when N iseven-numbered, this indicates N/2.

In Read mode, for example, if five charge pump stages operate inparallel, output switches of the five charge pump stages are eachconnected to a “b” position and input switches of (N−4) stages are eachconnected to the “b” position. All other switches are connected to the“a” position. In standby mode, for example, only three stages operate,in which case, input switches of (N−2) stages are each connected to the“b” position and all other switches are connected to the “a” position.

Charge pump circuit elements per stage are shown in FIG. 5.

This Dickson-type charge pump circuit free from substrate effects is acircuit shown in Japanese Patent Application No. 2002-333033.

FIG. 6 is a diagram that shows the specifications of the charge pumpcircuit necessary to operate a 64-KB single MONOS-type EEPROM.

Negative high voltages of −8.5 V and −10.7 V are required for erase andwrite operations, respectively. Since Erase and Write modes utilize atunneling effect, magnitudes of erase and write currents are severalpicoamperes per bit (pA/bit). Therefore, a current supply capability notgreater than 10 μA⁻ suffices for an EEPROM capacity of 64 KB.

In this case, the negative high voltages of −8.5 V and −10.7 V aregenerated by operating all 13 pump cell stages in series.

A Vpp simulation waveform based on the worst conditions of Vdd=1.375 Vand Ta=95° C. is shown in FIG. 7.

A clock rate of 10.8 MHz is used, and a circuit element with a 1-MΩresistance (at a 0V-Vpp terminal connection) for obtaining an outputsupply current of 10 μA or more, and a circuit element with a 1000-pFcapacitance equivalent to 64 KB of memory are connected as loads at aVpp output terminal. Also, the Vpp detector circuit is turned off toconfirm charge pump performance.

FIG. 7 indicates that a stepped-up voltage of at least −10.7 V can begenerated at the Vpp output terminal.

Next, a voltage of −2 V that is equal to or smaller than memoryinformation erase voltage Vt is required in Read mode. If a readingclock rate is 30 MHz and a selected memory gate (Mg) capacitance is 2 pF(equivalent to 128 bytes), the output supply current required is 120 μA,as shown in expression (1).2×2×10⁻¹²×30×10⁶=120×10⁻⁶  (1)

Ten pump cells at charge pump front and rear stages (i.e., the 5th to6th stages and 9th to 13th stages, respectively) are operated inparallel to compose a reading charge pump circuit for generating thevoltage of −2 V at which a high supply current capability can beobtained.

A clock rate of 10.8 MHz is used, and for three pump cell stages not tobe used (i.e., the 6th to 8th stages), a logic circuit is composed so asnot to supply a clock.

In addition, an NMOS switch (SW56) for disconnecting the pump cells ofthe 5th and 6th stages, and an NMOS switch (SW513) for connecting thepump cells of the 6th and final 13th stages at respective outputs areprovided and the outputs of the pump cells of the 6th and 13th stagesare connected by turning SW56 off and SW513 on, respectively, by use ofa level shifter LVL1 that generates a Vdd-Vpp output.

Furthermore, NMOS 90 for setting 0 V as an input of the pump cell of the9th stage, an MNOS switch (SW89) for turning off the control signalsupplied from the pump cell of the 8th stage to the pump cell of the 9thstage, and a switch CMOS 90 for connecting the control signal to theclock are controlled via LVL1 so that −2 V is also output from the final13th stage.

Another Vpp simulation waveform based on the worst conditions ofVdd=1.375 V and Ta=95° C. is shown in FIG. 8. An Mg driver for turningon and off the 2-pF capacitance at 35 MHz at the 0V-Vpp terminalconnection is operated as a load of Vpp. Also, the Vpp detector circuitis operated to detect a voltage of −2V typ. (typical).

It can be seen from FIG. 8 that −2.00±0.15 V can be continuously outputduring the 35-MHz read operation with an output supply current ofIout=163.6 μA avr. (average: measured simulation value).

Next, operation in standby mode is described. As mentioned above, instandby mode, Vpp also needs to be −1.5 V typ. and a maximum of 1 μA isset as a Vpp supply current with a leakage current taken intoconsideration.

Additionally, since current consumption in the entire charge pumpcircuit needs to be reduced in standby mode, charge pump circuit currentconsumption needs to be controlled below 10 μA.

The last four pump cell stages (i.e., the pump cells of the 10th to 13thstages) are operated as the charge pump circuit in standby mode, and forthe other nine stages (the 1st to 9th stages), a logic circuit iscomposed so as not to supply a clock.

In addition, NMOS 100 for setting 0 V as an input of the pump cell ofthe 10th stage, an MNOS switch (SW910) for turning off the controlsignal supplied from the pump cell of the 9th stage to the pump cell ofthe 10th stage, and a switch CMOS 100 for connecting the control signalto the clock are controlled via LVL2.

Furthermore, clock driver capabilities of the four pump cell stages tobe operated are switched and thus the through-current generated duringcharge capacitance driving is suppressed to reduce circuit currentconsumption.

Also, the clock generator circuit is deactivated and a Vpp detectionsignal is input as the clock supplied to the charge pump. The Vppdetection signal, as mentioned above, changes from 0 V to Vdd at aspecified voltage or less, and changes from Vdd to 0 V at the specifiedvoltage or more, whereby the signal can be used as the clock.

Thus, the current consumed in the clock generator circuit can besuppressed to almost zero, and this means that the total currentconsumption in the charge pump circuit can be reduced.

Yet another Vpp simulation waveform based on conditions (Vdd=1.375 V,Ta=95° C.) under which Vpp output capabilities decrease to the lowestlevel is shown in FIG. 9.

Since Vpp DET indicates that Vpp fluctuates from −1.33 V to −1.346 V, itcan be seen that Vpp DET is functioning as the charge pump clock.

Current consumption in the entire charge pump circuit totals 7 μA (4 μAin the charge pump, and 3 μA in the Vpp detector circuit). Thisindicates that reduction in current consumption has been achieved.

The legend used in the drawings accompanying this application is shownbelow.

-   -   CG . . . Control gate, MG . . . Memory gate, Select . . .        Selected region, H-Z . . . High impedance, E/W . . .        Erase/Write, Read . . . Readout, Write . . . Writing, Stby . . .        Standby, IL . . . Leakage current.

1. A charge pump circuit comprising: an N number of stages of basic pumpcells connected to supply a control voltage for data readout, writing,and erasure of a non-volatile memory; wherein, when reading out datafrom the non-volatile memory, said charge pump circuit selects, fromsaid N number of stages of basic pump cells, one pair of basic pumpcells consisting of stages not exceeding N/2 stages, and operates theselected basic pump cells in parallel.
 2. The charge pump circuitaccording to claim 1, wherein: said charge pump circuit operates thebasic pump cells of said N number of stages in series when performingdata erasing/writing operations on the non-volatile memory.
 3. Thecharge pump circuit according to claim 1, wherein: when the non-volatilememory is in a standby mode, said charge pump circuit operates, amongsaid N number of stages of basic pump cells, only basic pump cells ofstages not exceeding said N number of stages.
 4. A charge pump circuitsystem, comprising: a charge pump circuit controlled by two kinds ofdifferent voltages, said circuit having an N number of stages of basicpump cells connected to each other; and a detector circuit that judgeswhether or not an output voltage of said charge pump circuit is inexcess of a desired threshold value, and generates the two kinds ofdifferent voltages according to the judgment; wherein said charge pumpcircuit is controlled by the two kinds of different voltages that saiddetector circuit generates.
 5. The charge pump circuit system accordingto claim 4, wherein: said charge pump circuit supplies a voltage thatcontrols data readout, writing, and erasure of a non-volatile memory;and when the non-volatile memory is in a standby mode, said charge pumpcircuit is controlled by the two kinds of different voltages that saiddetector circuit generates.
 6. The charge pump circuit according toclaim 1, further comprising a clock generator circuit that generates twokinds of different voltages at a fixed period and controls said chargepump circuit; wherein, when said charge pump circuit generates a voltagethat controls data erasure, writing, and readout of the non-volatilememory, said clock generator circuit changes the voltage-generatingperiod, and when said charge pump circuit generates a voltage thatcontrols standby of the non-volatile memory, said clock generatorcircuit changes driving capability.
 7. The charge pump circuit accordingto claim 2, further comprising a clock generator circuit that generatestwo kinds of different voltages at a fixed period and controls saidcharge pump circuit; wherein, when said charge pump circuit generates avoltage that controls data erasure, writing, and readout of thenon-volatile memory, said clock generator circuit changes thevoltage-generating period, and when said charge pump circuit generates avoltage that controls standby of the non-volatile memory, said clockgenerator circuit changes driving capability.
 8. The charge pump circuitaccording to claim 3, further comprising a clock generator circuit thatgenerates two kinds of different voltages at a fixed period and controlssaid charge pump circuit; wherein, when said charge pump circuitgenerates a voltage that controls data erasure, writing, and readout ofthe non-volatile memory, said clock generator circuit changes thevoltage-generating period; and when said charge pump circuit generates avoltage that controls standby of the non-volatile memory, said clockgenerator circuit changes driving capability.
 9. The charge pump circuitsystem according to claim 4, further comprising a clock generatorcircuit that generates two kinds of different voltages at a fixed periodand controls said charge pump circuit; wherein, when said charge pumpcircuit generates a voltage that controls data erasure, writing, andreadout of the non-volatile memory, said clock generator circuit changesthe voltage-generating period, and when said charge pump circuitgenerates a voltage that controls standby of the non-volatile memory,said clock generator circuit changes driving capability.
 10. The chargepump circuit according to claim 1, wherein the basic pump cells ofstages not exceeding N/2 stages that are to be operated in parallel arebasic pump cells in a first half which includes a first stage of saidcharge pump circuit, and basic pump cells in a second half whichincludes a final stage of said charge pump circuit, and outputs of thesetwo sets of basic pump cells are combined.
 11. The charge pump circuitaccording to claim 3, wherein the basic pump cells of stages notexceeding N/2 stages are the basic pump cells in a second half of saidcharge pump circuit.
 12. The charge pump circuit according to claim 10,further comprising a clock generator circuit that generates two kinds ofdifferent voltages at a fixed period and controls said charge pumpcircuit; wherein said clock generator circuit supplies neither of thetwo kinds of different voltages to basic pump cells not to be operated.13. The charge pump circuit according to claim 11, further comprising aclock generator circuit that generates two kinds of different voltagesat a fixed period and controls said charge pump circuit; wherein saidclock generator circuit supplies neither of the two kinds of differentvoltages to basic pump cells not to be operated.
 14. A non-volatilememory with semiconductor storage elements arrayed in a matrix form,said non-volatile memory further including the charge pump circuitaccording to claim
 12. 15. A non-volatile memory with semiconductorstorage elements arrayed in a matrix form, said non-volatile memoryfurther including the charge pump circuit according to claim
 13. 16. Thenon-volatile memory according to claim 14, wherein an MONOS-structuredmemory cell is used in each of the semiconductor storage elements. 17.The non-volatile memory according to claim 15, wherein anMONOS-structured memory cell is used in each of the semiconductorstorage elements.